In active power management (APM) schemes the short term control of processor clock frequencies and core supply voltage (Vdd) are managed to thereby minimise power consumption in an active mode. Active power management is generally a fast power management component, where clock frequencies and voltages may need to be modified every few hundred microseconds. Decisions are based on short term application needs.
Clock frequency is usually phase-locked to a crystal reference using a PLL and the generated clock period varies by only 1 or 2%.
Supply voltage must have sufficient margin to guarantee functionality in spite of dynamic fluctuations that depend on the supply circuitry's ability to respond to changes in load that in turn depend on the application software that the processor is running.
The aim of the invention is to remove or reduce the need for such margin—thus lowering power consumption.